Quantum computing (QC) research and development have reached an extremely exciting point. Decades of research by academia worldwide has brought us to the point where the commercial world is widely engaged. Despite this progress, there still exist major challenges for the development of practical and useful quantum computers. One of these challenges is the necessity of operating quantum processors at deep cryogenic temperatures [Krinner2019]. In fact, it is not trivial to generate the sophisticated control sequences made of multiple-channel high-frequency signals at room temperature and timely deliver them to a quantum system which is located in a fairly inaccessible and vacuum-tight cryostat. 
 
A promising solution is based on the realisation of reliable cryogenic electronics that could leverage the vast existing manufacturing infrastructure currently dedicated to conventional integrated circuits (IC), i.e. the Complementary Metal Oxide Semiconductor (CMOS) technology. Cryo-CMOS [Pauka2021] could be a key enabler for the scaling of the main QC platforms because it would make it possible to tightly integrate control, readout and quantum protocols by avoiding the so-called interconnect bottleneck [Xue2021] with the room temperature control instrumentation. However, the operation of CMOS electronics at deep cryogenic temperatures requires stringent power management considerations, as well as a knowledge of the local environmental conditions of operation. In fact, each sub-component in a complex chip architecture may experience different local temperatures (even on the same chip) depending on the performed function and the amount of self-heating generated [Hart2021]. Such temperatures may all substantially deviate from the base temperature of the cryostat, and real-life operation conditions create a significant departure from what can be modelled using traditional circuit simulation methods.
 
This PhD will focus on the development of experimental techniques for accurate on-chip thermal assessment and management. The student will address the following critical challenges:

1. Development of novel on-die thermometry techniques using diodes, transistor gate electrodes and CMOS-compatible superconductors.
2. Chip-scale thermal mapping based on local heat sources and sensors under realistic operational conditions for quantum computing.
3. Thermally accurate circuit modelling aimed at both quantum and classical chip designs 

This project is part of a long-standing collaboration among three key players of the UK quantum landscape:

1. the Quantum Technology Department at the National Physical Laboratory (London) 
2. Quantum Motion Technologies (London), a rapidly growing start-up enterprise which develops silicon-based quantum systems
3. the Physics Department at the University of Strathclyde

The student is expected to carry out most of the research activities in Strathclyde and will become a member of the Semiconductor Quantum Electronics (SEQUEL) Lab. However, extended stays at the other partner institutions for training purposes will be encouraged and funded.

Further information

EPSRC Centre for Doctoral Training in Applied Quantum Technologies